It is known to design output buffers to control the slope of the voltage (dV/dt) when driving capacitive loads. However, when driving an inductive load driven by a pulse width modulated (PWM) waveform the known slope control circuitry is ineffective. The output field effect transistor (FET) gates are typically controlled by driving them with integrated RC networks to slow turn-on. Turn-off is deliberately made fast to avoid shoot-thru currents which occur when both output FETs are on at the same time.